- Concrete Standard Specifications (Design), 1996
- Concrete Standard Specifications (Verification of structural performance), 2002
- Concrete Standard Specifications (Design), 2007
- Design standards for railway structure (concrete structure), 1999
- Design standards for railway structure (concrete structure), 2004
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| Figure 1 Input of limit state design |
- Focus points for frame element
- Detail input list for limit state verification
- Detail input property for limit state verification
- Load for limit state verification
- Limit state verification list (Figure 3)
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| Figure 2 Input of focus point | Figure 3 Detail input list for verification of limit state desitn |
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| Figure 4 Detail input property for verification of limit state design | Figure 5 Load for verification of limit state design |
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| Figure 6 Verification list of limit state design |
The verification list of figure5 above is the unit for verification. The structure is as follosings.
[Verification list] ＝ [Focus points] ＋ [Detail input list] ＋ [Load definition]
Since there are a lot of input in the detail input list, input is performed in the special screen (Figure 4).
Since the several load cases can be specified at the same time in the load for verification, a lot of load cases can be verified in one limit state design list.
The verification results will be displayed at the rate like Figure 7, 8. Figure 7 is the summery. In this summary table, the strict results will be extracted and displayed from each verification. The detail results for each verification are as figure 8 below. Clicking the fields of rate in both figures can sort them in both ascending order and decending order.
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| Figure 7 Verification and summary table of limit state design | Figure 8 Verification result of limit state design |
Setting for repot output is performed as shown in figure 9. The detailed calculation sheet including the calculation formula can be output. Since the number of paper for output will be increased, the items to output can be selected.
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| Figure 9 Setting of reoirt output of limit state design |
